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-- Company: 
-- Engineer: 
-- 
-- Create Date:    
-- Design Name: 
-- Module Name:    SerialInterface - beh 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity SerialInterface is
   Port ( 
      Clk: in  std_logic;
      RESET: in  std_logic;
      rx_wire: in  std_logic;
      tx_wire: out  std_logic;
      );
end SerialInterface;

architecture beh of SerialInterface is
   type state_type is (idle, write_char1, write_charx);
   signal state_reg, state_next: state_type;

   signal tx_full, rx_empty, rx_full: std_logic;
   signal ascii_receive_data: std_logic_vector(7 downto 0);
   signal ascii_send_data: std_logic_vector(7 downto 0);

   signal send_one_byte : std_logic;
   signal read_byte : std_logic;

   begin

-- 9600 with a 50MHz clock requires 50,000,000/(16*9600) = 50,000,000/153,600 = 326
   UARTComponent: entity work.UARTUnit(beh)
      generic map (BAUDGEN_CLOCK_TO_BAUD_MOD=>326, BAUDGEN_REG_SIZE=>12, DATA_BITS=>8, STOP_BITS_TICKS=>16, 
         RX_FIFO_NUM_ADDR_BITS=>2, TX_FIFO_NUM_ADDR_BITS=>2)
      port map (clk=>Clk, reset=>RESET, rd_uart=>read_byte, wr_uart=>send_one_byte, rx_wire=>rx_wire,
         tx_loc_sys_data=>ascii_send_data, tx_full=>tx_full, rx_empty=>rx_empty, rx_full=>rx_full, 
         rx_loc_sys_data=>ascii_receive_data, tx_wire=>tx_wire);

-- ===========================================================================================
-- STATE AND REGISTER LOGIC
-- ===========================================================================================
   process(Clk, RESET)
      begin
      if (reset = '1') then
         state_reg <= idle;
      elsif (Clk'event and Clk = '1') then
         state_reg <= state_next;
      end if; 
   end process;

-- ===========================================================================================
-- COMBINATIONAL BLOCK
-- ===========================================================================================
-- COMPLETE THIS STATE MACHINE
   process(state_reg)
      begin

      case state_reg is

-- =================================
-- If the receive buffer has a character, process it
         when idle =>


-- =================================
-- Write first character of string "HELLO"
         when write_char1 =>


-- =================================
-- Other states you may need
         when write_charx =>

      end case;
   end process;

end beh;