library ieee;
use ieee.std_logic_1164.all;

entity vga_sync_test is
	port(
		clk, reset: in std_logic;
		sw: in std_logic_vector(2 downto 0);
		hsync, vsync: out std_logic;
		rgb_8bit: out std_logic_vector(23 downto 0);
		vga_pixel_tick: out std_logic;
		blank: out std_logic;
		comp_sync: out std_logic
	);
end vga_sync_test;

architecture arch of vga_sync_test is
	signal rgb_reg: std_logic_vector(2 downto 0);
	signal video_on: std_logic;
	signal rgb: std_logic_vector(2 downto 0);
	signal p_tick: std_logic;
	
-- instantiate VGA sync circuit
	begin
	vga_sync_unit: entity work.vga_sync
		port map(clk=>clk, reset=>reset, hsync=>hsync,
			vsync=>vsync, comp_sync=>comp_sync, video_on=>video_on,
			p_tick=>p_tick, pixel_x=>open,
			pixel_y=>open);

	vga_pixel_tick <= p_tick;
--	rgb_8bit(0) <= rgb(0);
--	rgb_8bit(1) <= rgb(0);
--	rgb_8bit(2) <= rgb(0);
--	rgb_8bit(3) <= rgb(0);
--	rgb_8bit(4) <= rgb(0);
--	rgb_8bit(5) <= rgb(0);
--	rgb_8bit(6) <= rgb(0);
	rgb_8bit(7) <= rgb(0);
	
--	rgb_8bit(8) <= rgb(1);
--	rgb_8bit(9) <= rgb(1);
--	rgb_8bit(10) <= rgb(1);
--	rgb_8bit(11) <= rgb(1);
--	rgb_8bit(12) <= rgb(1);
--	rgb_8bit(13) <= rgb(1);
--	rgb_8bit(14) <= rgb(1);
	rgb_8bit(15) <= rgb(1);
	
--	rgb_8bit(16) <= rgb(2);
--	rgb_8bit(17) <= rgb(2);
--	rgb_8bit(18) <= rgb(2);
--	rgb_8bit(19) <= rgb(2);
--	rgb_8bit(20) <= rgb(2);
--	rgb_8bit(21) <= rgb(2);
--	rgb_8bit(22) <= rgb(2);
	rgb_8bit(23) <= rgb(2);

	process(clk, reset) -- rgb buffer
		begin
		if (reset = '1') then
			rgb_reg <= (others => '0');
		elsif (clk'event and clk = '1') then
			rgb_reg <= sw;
		end if;
	end process;
	
	rgb <= rgb_reg when video_on = '1' else "000";
	blank <= video_on; 

--	process(reset)
--		begin
--		if (reset='1') then
--			blank <= '0';
--		else
--			blank <= '1';
--		end if;
--	end process;

end arch;