entity BitGen is
   generic (
      SAM_RESULT_NB: integer := 11;
      FLIP_FREQ_NB: integer := 8;
      MAX_BSTR_LEN_NB: integer := 24;
      MAX_BSTR_ENROLL_LEN_NB: integer := 16;
      XMR_LEN_NB: integer := 4;
      VDC_NUMBITS_NB: integer := 8;
      VDC_NUMBITS_RANGE: integer := 128
      );
   port (
      Clk: in  std_logic;
      RESET: in std_logic;
      start: in std_logic;
      ready: out std_logic;
      init_state: in std_logic;
      volt_diff_f: in std_logic_vector(SAM_RESULT_NB-1 downto 0);
      volt_diff_s: in std_logic_vector(SAM_RESULT_NB-1 downto 0);
      VDT_true_threshold: in std_logic_vector(SAM_RESULT_NB-1 downto 0);
      --TOP_threshold_scaler_offset: in std_logic_vector(SAM_RESULT_NB-1 downto 0);
      TOP_num_bits: in std_logic_vector(MAX_BSTR_LEN_NB-1 downto 0);
      TOP_XMR: in std_logic_vector(XMR_LEN_NB-1 downto 0);
      TOP_bit_gen_done: out std_logic;
      TOP_bstr_cur_len: out std_logic_vector(MAX_BSTR_LEN_NB-1 downto 0);
      TOP_flip_frequency: in std_logic_vector(FLIP_FREQ_NB-1 downto 0);
      TOP_valid_bit_ready: out std_logic;
      TOP_invalid_bit_ready: out std_logic;
      TOP_redundant_bit_ready: out std_logic;
      TOP_secret_bit: out std_logic;
      TOP_bstr_buf_ready_int: in std_logic;
      TOP_bstr_buf_ready: out std_logic;
      TOP_bstr_buf_continue: in std_logic;
      TOP_enroll: in std_logic;
      TOP_authen: in std_logic;
      PDMC_start: out std_logic;
      PDMC_ready: in std_logic;
      PDMC_write_bit: out std_logic;
      PDMC_last_bit: out std_logic;
      PDMC_vb_in_store: out std_logic
      );
end BitGen;
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