--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:05:26 10/02/2013
-- Design Name:   
-- Module Name:   /data/jplusq/GF40LP/PG_PUF_DESIGN/Xilinx/LFSR_BitGenDriver/ISE/ISE/Main_tb.vhd
-- Project Name:  ISE
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Main
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Main_tb IS
END Main_tb;
 
ARCHITECTURE behavior OF Main_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Main
    PORT(
         Clk : IN  std_logic;
         RESET : IN  std_logic;
         TOP_start : IN  std_logic;
         TOP_ready : OUT  std_logic;
         TOP_continue : IN  std_logic;
         TOP_exhaustive_or_subset : IN  std_logic;
         pairing_row1 : OUT  std_logic_vector(5 downto 0);
         pairing_col1 : OUT  std_logic_vector(5 downto 0);
         pairing_row2 : OUT  std_logic_vector(5 downto 0);
         pairing_col2 : OUT  std_logic_vector(5 downto 0);
         TOP_Pairings_OverRunErr : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal RESET : std_logic := '0';
   signal TOP_start : std_logic := '0';
   signal TOP_continue : std_logic := '0';
   signal TOP_exhaustive_or_subset : std_logic := '0';

 	--Outputs
   signal TOP_ready : std_logic;
   signal pairing_row1 : std_logic_vector(5 downto 0);
   signal pairing_col1 : std_logic_vector(5 downto 0);
   signal pairing_row2 : std_logic_vector(5 downto 0);
   signal pairing_col2 : std_logic_vector(5 downto 0);
   signal TOP_Pairings_OverRunErr : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Main PORT MAP (
          Clk => Clk,
          RESET => RESET,
          TOP_start => TOP_start,
          TOP_ready => TOP_ready,
          TOP_continue => TOP_continue,
          TOP_exhaustive_or_subset => TOP_exhaustive_or_subset,
          pairing_row1 => pairing_row1,
          pairing_col1 => pairing_col1,
          pairing_row2 => pairing_row2,
          pairing_col2 => pairing_col2,
          TOP_Pairings_OverRunErr => TOP_Pairings_OverRunErr
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      RESET <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	
      RESET <= '0';
      TOP_exhaustive_or_subset <= '1';

      TOP_start <= '1';
      wait for Clk_period;
      TOP_start <= '0';

      for I in 0 to 3841 loop
         wait until TOP_ready = '1';

         TOP_continue <= '1';
         wait for Clk_period;
         TOP_continue <= '0';
      end loop;


      wait;
   end process;

END;