`timescale 1ns / 1ps
`define MEM_SIZE 8
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

module ryan_transparport_tb_v;

// Inputs
   reg clk;
   reg reset;
   reg dvTf;
   reg dTf;

   // Outputs
   wire dvFf;
   wire dFf;

	// For debugging and file I/O
	reg [31:0] shft_reg;
	reg [31:0] word_in;
	reg [4:0] bit_counter;
	reg [4:0] word_in_counter;
	reg [31:0] RAM_1 [0:`MEM_SIZE-1];
	reg [4:0] word_index;	


// Instantiate the Unit Under Test (UUT)
   transparport uut (
      .ClkToFPGA(clk), 
      .Reset(reset), 
      .DataValidToFPGA(dvTf), 
      .DataToFPGA(dTf), 
      .DataValidFromFPGA(dvFf),
      .DataFromFPGA(dFf)
      );
		
   always begin
      #25 clk = ~clk;
   end

//	initial begin
//		$monitor("uhh = %h", word_in_copy);
//	end
	
   initial begin
      reset = 0;
      dvTf = 0;
      clk = 0;

// Wait 100 ns for global reset to finish
      #100 reset = 1;
      #50 reset = 0;

		word_in = 0;
		word_in_counter = 0;
		$readmemh("ryan_hex.txt", RAM_1);	

		#15 word_index = 0;
		while ( word_index < `MEM_SIZE )
		begin
			word_in = RAM_1[word_index];
//			word_in_copy = word_in;
			word_in_counter = 0;
			$display("Word In = %h", word_in);
			#50;

			while (word_in_counter != 5'b11111) begin
				dvTf = 1;
				dTf = word_in[0];
				word_in = word_in >> 1;
				word_in_counter = word_in_counter + 1;
				#50;
			end
			
			word_index = word_index+1;

		end
		
		// Read back stage		
		#50 dvTf = 0;
		word_index = 0;
		@(posedge dvFf);

		while ( word_index < `MEM_SIZE )
		begin
			bit_counter = 0;

			while (bit_counter != 5'b11111 ) begin
				@(posedge clk) shft_reg = shft_reg >> 1;
				shft_reg[31] = dFf;
				bit_counter = bit_counter+1;
			end 
			@(posedge clk) shft_reg = shft_reg >> 1;
			shft_reg[31] = dFf;

			$display("Word Out = %h", shft_reg);
			
			word_index = word_index+1;
			
		end
		
		#100 $stop;
	end 

endmodule