`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:41:59 09/20/2007 
// Design Name: 
// Module Name:    led 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module led(in, out);
    input [3:0] in;
    output [6:0] out;

	 wire [3:0] in;
 	 reg  [6:0] out;

    always @(in) begin
	    case (in) 
		    4'd0:  out = 7'b1110111;
          4'd1:  out = 7'b0010010;
          4'd2:  out = 7'b1011101;
 			 4'd3:  out = 7'b1011011;
			 4'd4:  out = 7'b0111010;
			 4'd5:  out = 7'b1101011;
			 4'd6:  out = 7'b1101111;
			 4'd7:  out = 7'b1010010;
			 4'd8:  out = 7'b1111111;
			 4'd9:  out = 7'b1111011;
			 4'd10: out = 7'b1111110;
			 4'd11: out = 7'b0101111;
			 4'd12: out = 7'b0001101;
			 4'd13: out = 7'b0011111;
			 4'd14: out = 7'b1101101;
			 4'd15: out = 7'b1101100;
	    endcase
	 end

endmodule